FIG. 1 shows an illustrative cross-section of an integrated circuit (not to scale). An integrated circuit is typically fabricated on the “front” side 102 of a silicon wafer 104. The integrated circuit is formed in stages, beginning with the careful introduction of impurities into localized regions of the silicon. The regions of impure (“doped”) silicon are termed “wells”. Small, heavily-doped wells are used as connection terminals of individual integrated device structures. The structure of a metal-oxide-semiconductor field effect transistor (MOSFET) includes two closely-spaced wells, with a conductive (often metallic) “gate” layer deposited on the front side 106 of the wafer 104 between the wells. (A thin oxide layer separates the gate from the silicon, hence the description “metal-oxide-semiconductor”). The conductivity of the silicon between the closely-spaced wells (the “channel”) can be changed by applying a voltage to the gate; this provides the controlled switching behavior that allows the device to operate as a transistor.
Once the transistors and other circuit components have been formed, a series of layers 108 are added to interconnect the circuit components. These layers include conductors that “wire” the components together, and insulation that protects and separates the conductors. The conductive materials in the layers 108 are opaque, but it has been discovered that the integrated circuit can be studied from the “back” side 106 of the wafer 104. Material may be ground away from the back side 106 to thin the wafer 104, thereby increasing its transparency.
Integrated circuits have microscopic dimensions, which make them difficult to test and characterize. Tsang, Kash, and Vallett present a new technique for measuring integrated circuit parameters in “Picosecond imaging circuit analysis,” IBM J Res. Develop., Vol. 44, No. 4, July 2000, which is hereby incorporated by reference. Some applications of what Tsang, et al, call their “PICA” technique are outlined by Lundquist and McManus in “Characterize gate-level transistor performance with PICA,” Semiconductor International, July 2001, which is also incorporated herein by reference. Among these applications are the measurement of propagation delays and relative timing parameters in circuits. Such applications may prove invaluable in quick pinpointing of the precise nature and location of faults.
The PICA technique relies on a combination of physical phenomena that are present in modem digital circuits. First, the MOSFETs employed in digital circuits typically operate in the saturation region of their current-voltage curves when “ON”. In this region, very high electric fields exist in the channel. Charge carriers (i.e., electrons and holes) can quickly gain a significant amount of kinetic energy in such electric fields, and indeed, many “hot” carriers are generated in this manner when current flows through the channel. A variety of scattering and recombination mechanisms may strip the energy from “hot” carriers, and in so doing, may trigger the emission of a photon of light. The light is emitted over a wide range of frequencies, but the infrared band of the spectrum is particularly significant because silicon is relatively transparent there.
The upshot is that current-carrying transistors in modem digital circuits emit infrared light. FIG. 1 represents the emission of infrared light as wavy lines originating from the transistor channels 110, 112.
One of the key factors to the success of highly integrated digital circuits is the use of complementary metal-oxide-semiconductor (CMOS) technology. CMOS technology consumes a dramatically smaller amount of current (and hence power) than other transistor technologies. The reduction in current is a consequence of pairing p-type MOSFETs with n-type MOSFETs, so that one of the transistors is “OFF” when the other is “ON”.
See, for example, FIG. 2, which shows a CMOS inverter. When the input voltage VIN is high (close to the supply voltage VDD), this puts the p-type MOSFET 202 in the “OFF” state, and puts the n-type MOSFET 204 in the “ON” state. The output voltage VOUT is pulled low (close to ground). Conversely, when VIN is low, transistor 202 is “ON” and transistor 204 is “OFF”, causing VOUT to be pulled high. Except briefly in the midst of VIN transitions between high and low voltages, one of the transistors is always “OFF”, so there is no steady-state current consumption. Only during transitions between states does any current flow occur. Because current flow is indicative of a switching transition, and because infrared light emission is indicative of current flow, we can use photon detection to measure the timing parameters of switching in digital circuits.
However, accurate extraction of timing parameters from PICA measurements is not straightforward. Photon emission is a statistical process, and it is expected that the probability of detected photon emission for current VLSI technology is on the order of 10−9 infrared photons per switching event per micron of channel width. To get a statistically useful measurement, many switching events must be generated, and the timing of the separately detected photons must be correlated with a repeatable trigger. The relative timing of the photons can be plotted as a histogram, and the peak of the histogram may be used to determine the timing of the transistor's switching transition relative to the trigger. Unfortunately, the histograms are “noisy” as a result of the granularity of the events (i.e., either a photon is detected, or it is not detected) and the rarity of events. The noise makes the measurements difficult to interpret. The histograms gradually approach a smooth curve if the measurements are taken over a sufficiently long period of time, but this is not expected to be feasible for small width devices or devices that switch infrequently relative to the clock frequency. Accordingly, an objective method of extracting circuit parameters from picosecond-scale photon timing measurements is desirable.